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| author |   Chen Wang <unicorn_wang@outlook.com> | 2024-01-30 09:50:51 +0800 |
|---|---|---|
| committer |   Inochi Amaoto <inochiama@outlook.com> | 2024-02-23 12:38:03 +0800 |
| commit | 08573ba006ab7bc29c183e0b3c362a0b34f1d87b (patch) | |
| tree | 96f207606b7d237d429549ee4373f2e5224379c8 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | riscv: dts: add reset generator for Sophgo SG2042 SoC (diff) | |
| download | wireguard-linux-08573ba006ab7bc29c183e0b3c362a0b34f1d87b.tar.xz wireguard-linux-08573ba006ab7bc29c183e0b3c362a0b34f1d87b.zip | |
riscv: dts: add resets property for uart node
Add resets property for uart0 for completeness, although it is
deasserted by default.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Inochi Amaoto <inochiama@outlook.com>
Link: https://lore.kernel.org/r/807f75e433a0f900da40ebb6a448349c98580072.1706577450.git.unicorn_wang@outlook.com
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions