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author | 2022-12-07 17:24:53 +0000 | |
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committer | 2022-12-07 17:24:53 +0000 | |
commit | 122d851b07116b30fbee99281d907c33a43f57c9 (patch) | |
tree | 532aaaa0eb0b7edcffe0207f1eb677bf0fa8bcf8 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | ASoC: Intel: Skylake: Topology and shutdown fixes (diff) | |
parent | ASoC: Intel: sof_realtek_common: set ret = 0 as initial value (diff) | |
download | wireguard-linux-122d851b07116b30fbee99281d907c33a43f57c9.tar.xz wireguard-linux-122d851b07116b30fbee99281d907c33a43f57c9.zip |
ASoC: Intel: boards: updates for SOF boards
Merge series from Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>:
One new JasperLake configuration, core refactoring between RT1316 and
RT1318 and a minor uninitialized variable corner case.
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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