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| author |   Max Gurtovoy <maxg@mellanox.com> | 2017-05-28 10:53:10 +0300 |
|---|---|---|
| committer |   Doug Ledford <dledford@redhat.com> | 2017-06-01 17:05:04 -0400 |
| commit | 1410a90ae449061b7e1ae19d275148f36948801b (patch) | |
| tree | c22be91288695b39252dbc938be7776994cab58a /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | RDMA/mlx4: Fix MAD tunneling when SRIOV is enabled (diff) | |
| download | wireguard-linux-1410a90ae449061b7e1ae19d275148f36948801b.tar.xz wireguard-linux-1410a90ae449061b7e1ae19d275148f36948801b.zip | |
net/mlx5: Define interface bits for fencing UMR wqe
HW can implement UMR wqe re-transmission in various ways.
Thus, add HCA cap to distinguish the needed fence for UMR to make
sure that the wqe wouldn't fail on mkey checks.
Signed-off-by: Max Gurtovoy <maxg@mellanox.com>
Acked-by: Leon Romanovsky <leon@kernel.org>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Doug Ledford <dledford@redhat.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions