diff options
| author |   Joshua Aberback <joshua.aberback@amd.com> | 2018-10-30 15:34:33 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2018-11-19 15:27:40 -0500 |
| commit | 14fee4ca84ecaa42aeada8ff404269e8c0a15efb (patch) | |
| tree | 9eebbb67e68aefc326071bc60b400259e685e82f /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/amd/display: get tail pipe before aquire free pipe (diff) | |
| download | wireguard-linux-14fee4ca84ecaa42aeada8ff404269e8c0a15efb.tar.xz wireguard-linux-14fee4ca84ecaa42aeada8ff404269e8c0a15efb.zip | |
drm/amd/display: Adjust stream enable sequence
[Why]
We observed an issue where a display would not accept programming of
the ignore_MSA_timing_param bit if the stream was blanked.
[How]
move enable_stream_features from enable_link_dp to
core_link_enable_stream, after unblank_stream
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions