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author | 2024-03-08 15:21:46 -0800 | |
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committer | 2024-03-08 15:24:45 -0800 | |
commit | 151c31ee79cd4d253eb3fc2959c2d461dcdd5767 (patch) | |
tree | 3a1c282e41320bf5764a2bedd523c513fae2a8bd /tools/perf/scripts/python/export-to-postgresql.py | |
parent | Linux 6.8-rc1 (diff) | |
parent | clk: meson: Add missing clocks to axg_clk_regmaps (diff) | |
download | wireguard-linux-151c31ee79cd4d253eb3fc2959c2d461dcdd5767.tar.xz wireguard-linux-151c31ee79cd4d253eb3fc2959c2d461dcdd5767.zip |
Merge tag 'clk-meson-v6.9-1' of https://github.com/BayLibre/clk-meson into clk-amlogic
Pull Amlogic clk driver update from Jerome Brunet:
- Fix clock listing Oops on Amlogic axg
* tag 'clk-meson-v6.9-1' of https://github.com/BayLibre/clk-meson:
clk: meson: Add missing clocks to axg_clk_regmaps
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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