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authorStephen Boyd <sboyd@kernel.org>2024-03-08 15:21:46 -0800
committerStephen Boyd <sboyd@kernel.org>2024-03-08 15:24:45 -0800
commit151c31ee79cd4d253eb3fc2959c2d461dcdd5767 (patch)
tree3a1c282e41320bf5764a2bedd523c513fae2a8bd /tools/perf/scripts/python/export-to-postgresql.py
parentLinux 6.8-rc1 (diff)
parentclk: meson: Add missing clocks to axg_clk_regmaps (diff)
downloadwireguard-linux-151c31ee79cd4d253eb3fc2959c2d461dcdd5767.tar.xz
wireguard-linux-151c31ee79cd4d253eb3fc2959c2d461dcdd5767.zip
Merge tag 'clk-meson-v6.9-1' of https://github.com/BayLibre/clk-meson into clk-amlogic
Pull Amlogic clk driver update from Jerome Brunet: - Fix clock listing Oops on Amlogic axg * tag 'clk-meson-v6.9-1' of https://github.com/BayLibre/clk-meson: clk: meson: Add missing clocks to axg_clk_regmaps
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