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| author |   Charlene Liu <Charlene.Liu@amd.com> | 2025-02-28 08:02:20 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2025-03-18 14:03:47 -0400 |
| commit | 15b959534a39530a21d378190557cc8d1eab7b09 (patch) | |
| tree | da002f5bfdc3d0e835b9b78edc5e20250d6434e0 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/amd/display: Update static soc table (diff) | |
| download | wireguard-linux-15b959534a39530a21d378190557cc8d1eab7b09.tar.xz wireguard-linux-15b959534a39530a21d378190557cc8d1eab7b09.zip | |
drm/amd/display: Use DPM table clk setting for dml2 soc dscclk
[WHY]
Not like dppclk/dispclk, dml2 will calculate the minimum required clocks.
For dscclk, it is used for pure comparision.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions