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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2017-04-03 11:45:43 +0200 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2017-04-03 06:32:54 -0400 |
| commit | 1cd9028027c7a7c10b774df698c3cfafec6aa67d (patch) | |
| tree | 2c5e4dcde7176ae285741ce82bedb4a3673b642e /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: r8a7791: Correct parent of SSI[0-9] clocks (diff) | |
| download | wireguard-linux-1cd9028027c7a7c10b774df698c3cfafec6aa67d.tar.xz wireguard-linux-1cd9028027c7a7c10b774df698c3cfafec6aa67d.zip | |
ARM: dts: r8a7793: Correct parent of SSI[0-9] clocks
The SSI-ALL gate clock is located in between the P clock and the
individual SSI[0-9] clocks, hence the former should be listed as their
parent.
Fixes: 072d326542e49187 ("ARM: dts: r8a7793: add MSTP10 clocks to device tree")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions