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| author |   Xing Zheng <zhengxing@rock-chips.com> | 2016-11-01 11:22:06 +0800 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2016-11-02 00:24:11 +0100 |
| commit | 1dfbec3905548a0cbc820a62e1d8adee1c80bd41 (patch) | |
| tree | 84391beaab8316b28c46765605013109d1d35208 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: rockchip: Use clock ids for cpu and peri clocks on rk3066 (diff) | |
| download | wireguard-linux-1dfbec3905548a0cbc820a62e1d8adee1c80bd41.tar.xz wireguard-linux-1dfbec3905548a0cbc820a62e1d8adee1c80bd41.zip | |
clk: rockchip: optimize 800MHz and 1GHz pll rates on RK3399
Usually, the 800MHz and 1GHz are supplied for CPLL and NPLL in the RK3399.
But dues to the carelessly copying from RK3036 when the RK3399 bringing up,
the refdiv == 6, it will increase the lock time, and it is not an optimal
configuration.
Let's fix them for the lock time and jitter are lower:
800 MHz:
- FVCO == 2.4 GHz, revdiv == 1.
1 GHz:
- FVCO == 3 GHz, revdiv == 1.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions