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| author |   Sibi Sankar <quic_sibis@quicinc.com> | 2022-02-09 23:15:57 +0530 |
|---|---|---|
| committer |   Bjorn Andersson <bjorn.andersson@linaro.org> | 2022-02-23 13:11:36 -0600 |
| commit | 1e8853c698276d20cdee99a8019f9f5e54c5c0a1 (patch) | |
| tree | 2f52fbe230b697cc6216c9aeffdf64102a1ae33f /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider (diff) | |
| download | wireguard-linux-1e8853c698276d20cdee99a8019f9f5e54c5c0a1.tar.xz wireguard-linux-1e8853c698276d20cdee99a8019f9f5e54c5c0a1.zip | |
arm64: dts: qcom: sc7280: Add cpu OPP tables
Add OPP tables required to scale DDR/L3 per freq-domain on SC7280 SoCs.
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1644428757-25575-1-git-send-email-quic_sibis@quicinc.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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