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author | 2021-10-15 13:14:20 +0200 | |
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committer | 2021-10-21 10:37:10 +0200 | |
commit | 211cde4f5817dc88ef7f8f2fa286e57fbf14c8ee (patch) | |
tree | ad536096d731c315a8dd32a05cfa9ad09893ed4c /tools/perf/scripts/python/export-to-postgresql.py | |
parent | serial: stm32: update throttle and unthrottle ops for dma mode (diff) | |
download | wireguard-linux-211cde4f5817dc88ef7f8f2fa286e57fbf14c8ee.tar.xz wireguard-linux-211cde4f5817dc88ef7f8f2fa286e57fbf14c8ee.zip |
serial: 8250: fix racy uartclk update
Commit 868f3ee6e452 ("serial: 8250: Add 8250 port clock update method")
added a hack to support SoCs where the UART reference clock can
change behind the back of the driver but failed to add the proper
locking.
First, make sure to take a reference to the tty struct to avoid
dereferencing a NULL pointer if the clock change races with a hangup.
Second, the termios semaphore must be held during the update to prevent
a racing termios change.
Fixes: 868f3ee6e452 ("serial: 8250: Add 8250 port clock update method")
Fixes: c8dff3aa8241 ("serial: 8250: Skip uninitialized TTY port baud rate update")
Cc: stable@vger.kernel.org # 5.9
Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Tested-by: Serge Semin <fancer.lancer@gmail.com>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Johan Hovold <johan@kernel.org>
Link: https://lore.kernel.org/r/20211015111422.1027-2-johan@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions