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| author |   Bjorn Helgaas <bhelgaas@google.com> | 2016-10-12 11:14:58 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2016-10-12 11:14:58 -0500 |
| commit | 22c7e1d4b48f61138a9e81270beaf73e98099adf (patch) | |
| tree | fc570fe0b5031dee9b315903c44afb890f92c617 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Merge branches 'pci/host-aardvark', 'pci/host-altera', 'pci/host-iproc', 'pci/host-mvebu', 'pci/host-rcar', 'pci/host-rockchip', 'pci/host-tegra', 'pci/host-xgene' and 'pci/host-xilinx' into next (diff) | |
| parent | PCI: designware-plat: Remove unused platform data (diff) | |
| download | wireguard-linux-22c7e1d4b48f61138a9e81270beaf73e98099adf.tar.xz wireguard-linux-22c7e1d4b48f61138a9e81270beaf73e98099adf.zip | |
Merge branch 'pci/host-designware' into next
* pci/host-designware:
PCI: designware-plat: Remove unused platform data
PCI: designware-plat: Add local struct device pointers
PCI: designware-plat: Remove redundant dw_plat_pcie.mem_base
PCI: designware: Swap order of dw_pcie_writel_unroll() reg/val arguments
PCI: designware: Uninline register accessors
PCI: designware: Export dw_pcie_readl_rc(), dw_pcie_writel_rc()
PCI: designware: Swap order of dw_pcie_writel_rc() reg/val arguments
PCI: designware: Simplify pcie_host_ops.readl_rc() and .writel_rc() interfaces
PCI: designware: Simplify dw_pcie_readl_unroll(), dw_pcie_writel_unroll()
PCI: designware: Rename dw_pcie_valid_config() to dw_pcie_valid_device()
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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