diff options
| author |   Dikshita Agarwal <dikshita@codeaurora.org> | 2021-04-02 12:06:35 +0200 |
|---|---|---|
| committer |   Mauro Carvalho Chehab <mchehab+huawei@kernel.org> | 2021-04-06 15:46:40 +0200 |
| commit | 255385ca433ce5ff621732f26a759211a27c8f85 (patch) | |
| tree | 35a9f35755638e58f275b10f5c1f7a2e6c746029 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | media: venus: core: Hook to V6 base registers when appropriate (diff) | |
| download | wireguard-linux-255385ca433ce5ff621732f26a759211a27c8f85.tar.xz wireguard-linux-255385ca433ce5ff621732f26a759211a27c8f85.zip | |
media: venus: hfi: Add a 6xx boot logic
This patch adds a 6xx specific boot logic. The goal is to share as much
code as possible between 3xx, 4xx and 6xx silicon.
We need to do a different write to WRAPPER_INTR_MASK with an additional
write to CPU_CS_H2XSOFTINTEN_V6 and CPU_CS_X2RPMh_V6.
The other writes are the same for 6xx and non-6xx silicon albeit at
different absolute relative locations to the base of the venus address
space.
Signed-off-by: Dikshita Agarwal <dikshita@codeaurora.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions