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| author |   Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> | 2020-09-11 21:47:09 -0700 |
|---|---|---|
| committer |   Santosh Shilimkar <santosh.shilimkar@oracle.com> | 2020-09-11 21:47:09 -0700 |
| commit | 25bafac9408f67873f03909401deecfb16974d84 (patch) | |
| tree | dcc5e7e0d602a77706cf8c67a54c3859c2269ab4 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | firmware: ti_sci: allow frequency change for disabled clocks by default (diff) | |
| download | wireguard-linux-25bafac9408f67873f03909401deecfb16974d84.tar.xz wireguard-linux-25bafac9408f67873f03909401deecfb16974d84.zip | |
dt-bindings: soc: ti: Update TI PRUSS bindings regarding clock-muxes
ICSS/ICSSG modules have an IEP clock mux that allow selection of
internal IEP clock from 2 clock sources.
ICSSG module has a CORE clock mux that allows selection of internal CORE
clock from 2 clock sources.
Add binding information for these 2 clock muxes.
Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions