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| author |   Dinh Nguyen <dinguyen@kernel.org> | 2022-01-06 17:53:31 -0600 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2022-02-09 13:18:48 -0600 |
| commit | 268a491aebc25e6dc7c618903b09ac3a2e8af530 (patch) | |
| tree | 23fc1267882b55a98c6610b1c949b446bf92258a /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | dt-bindings: usb: dwc2: add compatible "intel,socfpga-agilex-hsotg" (diff) | |
| download | wireguard-linux-268a491aebc25e6dc7c618903b09ac3a2e8af530.tar.xz wireguard-linux-268a491aebc25e6dc7c618903b09ac3a2e8af530.zip | |
arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"
The DWC2 USB controller on the Agilex platform does not support clock
gating, so use the chip specific "intel,socfpga-agilex-hsotg"
compatible.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions