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| author |   Dan Williams <dan.j.williams@intel.com> | 2022-11-29 10:48:59 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-12-03 13:40:17 -0800 |
| commit | 2905cb5236cba63a5dc8a83752dcc31f3cc819f9 (patch) | |
| tree | 7b5cd1bb0118b896d04813feef85e2f8692438ff /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | cxl/pci: add tracepoint events for CXL RAS (diff) | |
| download | wireguard-linux-2905cb5236cba63a5dc8a83752dcc31f3cc819f9.tar.xz wireguard-linux-2905cb5236cba63a5dc8a83752dcc31f3cc819f9.zip | |
cxl/pci: Add (hopeful) error handling support
Add nominal error handling that tears down CXL.mem in response to error
notifications that imply a device reset. Given some CXL.mem may be
operating as System RAM, there is a high likelihood that these error
events are fatal. However, if the system survives the notification the
expectation is that the driver behavior is equivalent to a hot-unplug
and re-plug of an endpoint.
Note that this does not change the mask values from the default. That
awaits CXL _OSC support to determine whether platform firmware is in
control of the mask registers.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/166974413966.1608150.15522782911404473932.stgit@djiang5-desk3.ch.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions