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| author |   Jason Gunthorpe <jgg@nvidia.com> | 2024-08-29 21:06:23 -0300 |
|---|---|---|
| committer |   Joerg Roedel <jroedel@suse.de> | 2024-09-04 11:39:03 +0200 |
| commit | 2910a7fa1be090fc7637cef0b2e70bcd15bf5469 (patch) | |
| tree | 8a8e2fde1ae893d3f6ae78db5c79c6f5e632e649 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | iommu/amd: Correct the reported page sizes from the V1 table (diff) | |
| download | wireguard-linux-2910a7fa1be090fc7637cef0b2e70bcd15bf5469.tar.xz wireguard-linux-2910a7fa1be090fc7637cef0b2e70bcd15bf5469.zip | |
iommu/amd: Do not set the D bit on AMD v2 table entries
The manual says that bit 6 is IGN for all Page-Table Base Address
pointers, don't set it.
Fixes: aaac38f61487 ("iommu/amd: Initial support for AMD IOMMU v2 page table")
Reviewed-by: Vasant Hegde <vasant.hegde@amd.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/14-v2-831cdc4d00f3+1a315-amd_iopgtbl_jgg@nvidia.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions