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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-06-20 15:57:36 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-07-01 11:35:08 +0200 |
| commit | 2918674704aad620215c41979a331021fe3f1ec4 (patch) | |
| tree | 99c349f4600eefd7c198943b498d950828c1fde0 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: dts: renesas: r9a07g044: Add missing hypervisor virtual timer IRQ (diff) | |
| download | wireguard-linux-2918674704aad620215c41979a331021fe3f1ec4.tar.xz wireguard-linux-2918674704aad620215c41979a331021fe3f1ec4.zip | |
arm64: dts: renesas: r9a07g054: Add missing hypervisor virtual timer IRQ
Add the missing fifth interrupt to the device node that represents the
ARM architected timer. While at it, add an interrupt-names property for
clarity,
Fixes: 7c2b8198f4f321df ("arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/834244e77e5f407ee6fab1ab5c10c98a8a933085.1718890849.git.geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions