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author | 2021-02-24 14:59:21 -0600 | |
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committer | 2021-02-24 14:59:21 -0600 | |
commit | 29b10c606f1a2caa3716f714edb533cbe8b2a20b (patch) | |
tree | e795f6db89889b039259d14199cf724776f58dc7 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | Merge branch 'remotes/lorenzo/pci/cadence' (diff) | |
parent | PCI: al: Remove useless dw_pcie_ops (diff) | |
download | wireguard-linux-29b10c606f1a2caa3716f714edb533cbe8b2a20b.tar.xz wireguard-linux-29b10c606f1a2caa3716f714edb533cbe8b2a20b.zip |
Merge branch 'pci/dwc'
- Always set DesignWare "TLP Digest" bit so generic code can enable ECRC
via the AER Capability (Vidya Sagar)
- Drop support for config space in DT 'ranges' (Rob Herring)
- Increase width of outbound iATU size to u64 (Shradha Todi)
- Add upper limit address for outbound iATU (Shradha Todi)
- Allow dwc-based drivers that don't override any default ops (Jisheng
Zhang)
- Drop unnecessary dw_pcie_ops from the al driver (Jisheng Zhang)
* pci/dwc:
PCI: al: Remove useless dw_pcie_ops
PCI: dwc: Don't assume the ops in dw_pcie always exist
PCI: dwc: Add upper limit address for outbound iATU
PCI: dwc: Change size to u64 for EP outbound iATU
PCI: dwc: Drop support for config space in 'ranges'
PCI: dwc: Work around ECRC configuration issue
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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