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| author |   Palmer Dabbelt <palmer@rivosinc.com> | 2024-03-13 07:30:33 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-03-13 07:30:33 -0700 |
| commit | 2b2ca354674bed0d0222ce1426d2d45b065ac1e8 (patch) | |
| tree | b36b271e9efce452423d4b0c7d26eea976e1a7b8 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Merge patch series "Support Andes PMU extension" (diff) | |
| parent | riscv: Set unaligned access speed at compile time (diff) | |
| download | wireguard-linux-2b2ca354674bed0d0222ce1426d2d45b065ac1e8.tar.xz wireguard-linux-2b2ca354674bed0d0222ce1426d2d45b065ac1e8.zip | |
Merge patch series "riscv: Use Kconfig to set unaligned access speed"
Charlie Jenkins <charlie@rivosinc.com> says:
If the hardware unaligned access speed is known at compile time, it is
possible to avoid running the unaligned access speed probe to speedup
boot-time.
* b4-shazam-merge:
riscv: Set unaligned access speed at compile time
riscv: Decouple emulated unaligned accesses from access speed
riscv: Only check online cpus for emulated accesses
riscv: lib: Introduce has_fast_unaligned_access()
Link: https://lore.kernel.org/r/20240308-disable_misaligned_probe_config-v9-0-a388770ba0ce@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions