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| author |   Johan Jonker <jbx6244@gmail.com> | 2020-04-28 22:30:03 +0200 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2020-05-19 10:17:51 +0200 |
| commit | 2b99e6196663199409540fb95798dba464e34343 (patch) | |
| tree | e4735ec869fc3ca354456b5a13ad30cc5f6669a6 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: dts: rockchip: add bus-width properties to mmc nodes for px30 (diff) | |
| download | wireguard-linux-2b99e6196663199409540fb95798dba464e34343.tar.xz wireguard-linux-2b99e6196663199409540fb95798dba464e34343.zip | |
arm64: dts: rockchip: fix pd_tcpc0 and pd_tcpc1 node position on rk3399
The pd_tcpc0 and pd_tcpc1 nodes are currently a sub node of pd_vio.
In the rk3399 TRM figure of the 'Power Domain Partition' and in the
table of 'Power Domain and Voltage Domain Summary' these power domains
are positioned directly under VD_LOGIC, so fix that in 'rk3399.dtsi'.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Caesar Wang <wxt@rock-chips.com>
Link: https://lore.kernel.org/r/20200428203003.3318-2-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions