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| author |   Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> | 2015-02-02 14:09:58 +0900 |
|---|---|---|
| committer |   Bjorn Helgaas <bhelgaas@google.com> | 2015-02-24 00:23:32 -0600 |
| commit | 2ea2a2734cd850d8d270022e9aaabc02a931c172 (patch) | |
| tree | 66c363e5d92a15716898762a3f9e33be86a686cf /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | PCI: rcar: Fix position of MSI enable bit (diff) | |
| download | wireguard-linux-2ea2a2734cd850d8d270022e9aaabc02a931c172.tar.xz wireguard-linux-2ea2a2734cd850d8d270022e9aaabc02a931c172.zip | |
PCI: rcar: Write zeroes to reserved PCIEPARL bits
The lower 7 bits of PCIEPARL are reserved. When we write to this register,
these bits must be 0.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions