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| author |   Lukasz Luba <l.luba@partner.samsung.com> | 2019-01-15 17:12:16 +0100 |
|---|---|---|
| committer |   Sylwester Nawrocki <s.nawrocki@samsung.com> | 2019-06-06 15:53:37 +0200 |
| commit | 2f57b95caf8f6db7a1295fc9940f91184ced912b (patch) | |
| tree | bd1bcbb0c045b36634ceb8a4af948261f52bcae2 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: samsung: add BPLL rate table for Exynos 5422 SoC (diff) | |
| download | wireguard-linux-2f57b95caf8f6db7a1295fc9940f91184ced912b.tar.xz wireguard-linux-2f57b95caf8f6db7a1295fc9940f91184ced912b.zip | |
clk: samsung: add new clocks for DMC for Exynos5422 SoC
This patch provides support for clocks needed for Dynamic Memory Controller
in Exynos5422 SoC. It adds CDREX base register addresses, new DIV, MUX and
GATE entries.
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions