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| author |   Rob Clark <robdclark@gmail.com> | 2016-10-13 12:43:17 -0400 |
|---|---|---|
| committer | Rob Clark <robdclark@gmail.com> | 2016-11-02 10:49:33 -0400 |
| commit | 31e4801aa2e59d4b42dc0fd42846a3aa7a6361af (patch) | |
| tree | e91f294bd03e0c480291531a9a1a1008d2542d20 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/msm: Set CLK_IGNORE_UNUSED flag for PLL clocks (diff) | |
| download | wireguard-linux-31e4801aa2e59d4b42dc0fd42846a3aa7a6361af.tar.xz wireguard-linux-31e4801aa2e59d4b42dc0fd42846a3aa7a6361af.zip | |
drm/msm/mdp5: handle non-fullscreen base plane case
If the bottom-most layer is not fullscreen, we need to use the BASE
mixer stage for solid fill (ie. MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT). The
blend_setup() code pretty much handled this already, we just had to
figure this out in _atomic_check() and assign the stages appropriately.
Also fix the case where there are zero enabled planes, where we also
need to enable BORDER_OUT.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions