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| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2023-10-09 16:22:03 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2023-10-13 16:26:32 +0300 |
| commit | 34d8311f4a1c464ae0ce4470f2e3932c1a40d83e (patch) | |
| tree | a96be1d5e15d91a5be98a4a00cbdd1c46584e7ee /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915/dsb: Correct DSB command buffer cache coherency settings (diff) | |
| download | wireguard-linux-34d8311f4a1c464ae0ce4470f2e3932c1a40d83e.tar.xz wireguard-linux-34d8311f4a1c464ae0ce4470f2e3932c1a40d83e.zip | |
drm/i915/dsb: Re-instate DSB for LUT updates
With all the known issues sorted out we can start to use
DSB to load the LUTs.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231009132204.15098-3-ville.syrjala@linux.intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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