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| author |   Florian Fainelli <f.fainelli@gmail.com> | 2021-10-20 11:48:51 -0700 |
|---|---|---|
| committer |   Marc Zyngier <maz@kernel.org> | 2021-10-20 20:06:33 +0100 |
| commit | 3578fd47137c405b6fb9f90e2e6d1654c71f5e1e (patch) | |
| tree | b73c1158e02dc806b1a4aba21ebe890490f731e2 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | irqchip/irq-bcm7038-l1: Gate use of CPU logical map to MIPS (diff) | |
| download | wireguard-linux-3578fd47137c405b6fb9f90e2e6d1654c71f5e1e.tar.xz wireguard-linux-3578fd47137c405b6fb9f90e2e6d1654c71f5e1e.zip | |
irqchip/irq-bcm7038-l1: Restrict affinity setting to MIPS
Only MIPS based platforms using this interrupt controller as first level
interrupt controller can actually change the affinity of interrupts by
re-programming the affinity mask of the interrupt controller and use
another word group to have another CPU process the interrupt.
When this interrupt is used as a second level interrupt controller on
ARM/ARM64 there is no way to change the interrupt affinity. This fixes a
NULL pointer de-reference while trying to change the affinity since
there is only a single word group in that case, and we would have been
overruning the intc->cpus[] array.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211020184859.2705451-6-f.fainelli@gmail.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions