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| author |   Radhakrishna Sripada <radhakrishna.sripada@intel.com> | 2023-03-01 12:10:49 -0800 |
|---|---|---|
| committer |   Jani Nikula <jani.nikula@intel.com> | 2023-03-20 10:59:54 +0200 |
| commit | 364ac7863fc161841e86388884bb7d5f4048031a (patch) | |
| tree | 0b8ece09bc5b502ac81fa557b8152b5952c74868 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Linux 6.3-rc3 (diff) | |
| download | wireguard-linux-364ac7863fc161841e86388884bb7d5f4048031a.tar.xz wireguard-linux-364ac7863fc161841e86388884bb7d5f4048031a.zip | |
drm/i915/mtl: Fix Wa_16015201720 implementation
The commit 2357f2b271ad ("drm/i915/mtl: Initial display workarounds")
extended the workaround Wa_16015201720 to MTL. However the registers
that the original WA implemented moved for MTL.
Implement the workaround with the correct register.
v3: Skip clock gating for pipe C, D DMC's and fix the title
Fixes: 2357f2b271ad ("drm/i915/mtl: Initial display workarounds")
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230301201053.928709-2-radhakrishna.sripada@intel.com
(cherry picked from commit 0188be507b973e36f637ba010a369057c8cb7282)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions