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| author |   Abel Vesa <abel.vesa@nxp.com> | 2022-11-07 16:50:06 +0800 |
|---|---|---|
| committer |   Abel Vesa <abel.vesa@linaro.org> | 2022-11-22 00:04:49 +0200 |
| commit | 36759c4fe217263a4688aabf384302afbe1004fa (patch) | |
| tree | a1b08abf04dbc0af2067a4b8b5f6f77592b96719 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: imx: pll14xx: Add 320 MHz and 640 MHz entries for PLL146x (diff) | |
| download | wireguard-linux-36759c4fe217263a4688aabf384302afbe1004fa.tar.xz wireguard-linux-36759c4fe217263a4688aabf384302afbe1004fa.zip | |
dt-bindings: clock: imx8mp: Add ids for the audio shared gate
All these IDs are for one single HW gate (CCGR101) that is shared
between these root clocks.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/1667811007-19222-2-git-send-email-shengjiu.wang@nxp.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions