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| author |   Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> | 2022-01-02 12:53:49 +0100 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> | 2022-01-23 18:04:02 +0100 |
| commit | 372d171cd9b472cff7852211195f211150bc27d2 (patch) | |
| tree | bce28283834c146eb9b0d7910e4f6490860f5c5a /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: dts: exynos: Align MAX77843 nodes with dtschema on TM2 (diff) | |
| download | wireguard-linux-372d171cd9b472cff7852211195f211150bc27d2.tar.xz wireguard-linux-372d171cd9b472cff7852211195f211150bc27d2.zip | |
arm64: dts: exynos: add necessary clock inputs in Exynos7
Exynos7 devicetree bindings require more input clocks for TOP0 and
PERIC1 clock controllers, than already provided. Existing DTS was not
matching the bindings, so let's update the DTS, even though the error
could be in the bindings.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20220102115356.75796-1-krzysztof.kozlowski@canonical.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions