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| author |   Wenjing Liu <wenjing.liu@amd.com> | 2024-01-18 15:14:15 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2024-01-31 17:29:58 -0500 |
| commit | 39079fe8e660851abbafa90cd55cbf029210661f (patch) | |
| tree | 606ea05c824e35141438eb4260be77f3b9216e9a /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/amd/display: Fix DPSTREAM CLK on and off sequence (diff) | |
| download | wireguard-linux-39079fe8e660851abbafa90cd55cbf029210661f.tar.xz wireguard-linux-39079fe8e660851abbafa90cd55cbf029210661f.zip | |
drm/amd/display: fix incorrect mpc_combine array size
[why]
MAX_SURFACES is per stream, while MAX_PLANES is per asic. The
mpc_combine is an array that records all the planes per asic. Therefore
MAX_PLANES should be used as the array size. Using MAX_SURFACES causes
array overflow when there are more than 3 planes.
[how]
Use the MAX_PLANES for the mpc_combine array size.
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Reviewed-by: Nevenko Stupar <nevenko.stupar@amd.com>
Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions