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| author |   Jouni Högander <jouni.hogander@intel.com> | 2024-04-09 11:57:59 +0300 |
|---|---|---|
| committer | Jouni Högander <jouni.hogander@intel.com> | 2024-04-11 12:09:48 +0300 |
| commit | 3a487d111d065f212f863f2327fdbd3fc311f363 (patch) | |
| tree | fcd1f25f822e2254a7213743aed6e1a03c3349a2 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915/mtl: Add DP FEC BS jitter WA (diff) | |
| download | wireguard-linux-3a487d111d065f212f863f2327fdbd3fc311f363.tar.xz wireguard-linux-3a487d111d065f212f863f2327fdbd3fc311f363.zip | |
drm/i915/psr: Use crtc_state->port_clock instead of intel_dp->link_rate
Intel_dp->link_rate is not yet set at this point. Instead use
crtc_state->port_clock.
Fixes: 0dd21f836983 ("drm/i915/psr: Silence period and lfps half cycle")
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240409085759.178235-1-jouni.hogander@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions