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| author |   Conor Dooley <conor.dooley@microchip.com> | 2023-06-15 23:50:14 +0100 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2023-06-22 14:23:52 -0700 |
| commit | 3c1b4758a9544cbaf38d052ad66a69618e920ceb (patch) | |
| tree | 47149899e25177d983ef53c32fb6168f3afd2614 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Linux 6.4-rc1 (diff) | |
| download | wireguard-linux-3c1b4758a9544cbaf38d052ad66a69618e920ceb.tar.xz wireguard-linux-3c1b4758a9544cbaf38d052ad66a69618e920ceb.zip | |
dt-bindings: riscv: cpus: add a ref the common cpu schema
To permit validation of RISC-V cpu nodes, "additionalProperties: true"
needs to be swapped for "unevaluatedProperties: false". To facilitate
this in a way that passes dt_binding_check, a reference to the cpu
schema is required.
Disallow the generic cache-op-block-size property that that drags in,
since the RISC-V CBO extensions do not require a common size, and have
individual properties.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20230615-dubiously-parasail-79d34cefedce@spud
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions