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| author |   Stephen Boyd <sboyd@kernel.org> | 2019-10-16 14:01:19 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-10-16 14:01:19 -0700 |
| commit | 3d883e896947cceeb0e290dfffe0bc16912c90ae (patch) | |
| tree | 44b434b298081c918ed28cfae2c2122199bb7092 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: at91: sam9x60: fix programmable clock (diff) | |
| parent | clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes (diff) | |
| download | wireguard-linux-3d883e896947cceeb0e290dfffe0bc16912c90ae.tar.xz wireguard-linux-3d883e896947cceeb0e290dfffe0bc16912c90ae.zip | |
Merge tag 'clk-meson-fixes-v5.4-1' of https://github.com/BayLibre/clk-meson into clk-fixes
Pull first round of amlogic clock fixes from Jerome Brunet:
- This fixes the clock rate propagation for the g12a cpu and gxbb adc clocks.
* tag 'clk-meson-fixes-v5.4-1' of https://github.com/BayLibre/clk-meson:
clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes
clk: meson: g12a: fix cpu clock rate setting
clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions