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| author |   Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2023-01-10 11:35:33 +0000 |
|---|---|---|
| committer | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2023-01-11 09:20:23 +0000 |
| commit | 3e95263dfb52d5e5b60fbdda51094c788c446f07 (patch) | |
| tree | c6c141f6be6e91ff75181c392c47c769ed17c894 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915/gt: Cover rest of SVG unit MCR registers (diff) | |
| download | wireguard-linux-3e95263dfb52d5e5b60fbdda51094c788c446f07.tar.xz wireguard-linux-3e95263dfb52d5e5b60fbdda51094c788c446f07.zip | |
drm/i915: Do not cover all future platforms in TLB invalidation
Revert to the original explicit approach and document the reasoning
behind it.
v2:
* DG2 needs to be covered too. (Matt)
v3:
* Full version check for Gen12 to avoid catching all future platforms.
(Matt)
v4:
* Be totally explicit on the Gen12 branch. (Andrzej)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> # v1
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230110113533.744436-1-tvrtko.ursulin@linux.intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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