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| author |   William Qiu <william.qiu@starfivetech.com> | 2023-07-17 10:30:39 +0800 |
|---|---|---|
| committer |   Conor Dooley <conor.dooley@microchip.com> | 2023-07-20 17:22:30 +0100 |
| commit | 3fcbcfc496f0cc08f9dc004a92915ce1cfb7ea95 (patch) | |
| tree | c4f82585be7a8368ff36df1ae76d5aeb0e597e12 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes (diff) | |
| download | wireguard-linux-3fcbcfc496f0cc08f9dc004a92915ce1cfb7ea95.tar.xz wireguard-linux-3fcbcfc496f0cc08f9dc004a92915ce1cfb7ea95.zip | |
riscv: dts: starfive: jh7110: Add syscon nodes
Add stg_syscon/sys_syscon/aon_syscon/PLL nodes for JH7110 SoC.
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions