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authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>2016-06-13 00:15:55 +0300
committerSimon Horman <horms+renesas@verge.net.au>2016-06-16 09:25:29 +0900
commit4018fba454602cc1d01a216352935d88582353f1 (patch)
tree0634cf301bf547df8566bdd515828480a75b7622 /tools/perf/scripts/python/export-to-postgresql.py
parentARM: dts: blanche: document Blanche board (diff)
downloadwireguard-linux-4018fba454602cc1d01a216352935d88582353f1.tar.xz
wireguard-linux-4018fba454602cc1d01a216352935d88582353f1.zip
ARM: dts: blanche: initial device tree
Add the initial device tree for the R8A7792 SoC based Blanche board. The board has 2 debug serial ports: SCIF0 and SCIF3; include support for them, so that the serial console can work. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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