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author | 2020-09-13 11:33:41 -0700 | |
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committer | 2020-09-13 11:33:43 -0700 | |
commit | 439a95a044223972a9128d32df7f78f56c99ef51 (patch) | |
tree | dffd5ea19bfa67568ed6b4d79348aca49926ee35 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | Merge tag 'dt64-schema-5.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt (diff) | |
parent | ARM: dts: alpine: Align GIC nodename with dtschema (diff) | |
download | wireguard-linux-439a95a044223972a9128d32df7f78f56c99ef51.tar.xz wireguard-linux-439a95a044223972a9128d32df7f78f56c99ef51.zip |
Merge tag 'dt-schema-5.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Various minor cleanups for ARM DTS
Cleanup ARM DTS to remove dtschema validation errors.
* tag 'dt-schema-5.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: alpine: Align GIC nodename with dtschema
ARM: dts: zx: Align L2 cache-controller nodename with dtschema
ARM: dts: tango: Align L2 cache-controller nodename with dtschema
ARM: dts: spear: Align L2 cache-controller nodename with dtschema
ARM: dts: qcom: Align L2 cache-controller nodename with dtschema
ARM: dts: prima: Align L2 cache-controller nodename with dtschema
Link: https://lore.kernel.org/r/20200911155509.1495-2-krzk@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
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