diff options
| author |   Neil Armstrong <neil.armstrong@linaro.org> | 2023-11-14 11:14:43 +0100 |
|---|---|---|
| committer |   Jerome Brunet <jbrunet@baylibre.com> | 2023-11-24 18:03:00 +0100 |
| commit | 439d3404addf1a1ee8ba6dc6becd555bce7faf98 (patch) | |
| tree | 9c7ed65e74f556845e733c017396c26d317a5f49 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | dt-bindings: clk: g12a-clkc: add CTS_ENCL clock ids (diff) | |
| download | wireguard-linux-439d3404addf1a1ee8ba6dc6becd555bce7faf98.tar.xz wireguard-linux-439d3404addf1a1ee8ba6dc6becd555bce7faf98.zip | |
dt-bindings: clock: g12a-clkc: add MIPI ISP & CSI PHY clock ids
Add MIPI ISP & CSI PHY clock ids to G12A clock bindings header
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Daniel Scally <dan.scally@ideasonboard.com>
Tested-by: Daniel Scally <dan.scally@ideasonboard.com>
Link: https://lore.kernel.org/r/20231114-topic-amlogic-upstream-isp-clocks-v1-1-223958791501@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions