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| author |   Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2017-07-28 23:13:13 +0200 |
|---|---|---|
| committer |   Kevin Hilman <khilman@baylibre.com> | 2017-08-01 12:33:47 -0700 |
| commit | 45631ea8b5d814845a9e3a246ea79c89d63bf786 (patch) | |
| tree | 54dfa8af3a9ed8ee1882f2040942626074ba2404 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: meson: add a node which describes the SRAM (diff) | |
| download | wireguard-linux-45631ea8b5d814845a9e3a246ea79c89d63bf786.tar.xz wireguard-linux-45631ea8b5d814845a9e3a246ea79c89d63bf786.zip | |
ARM: dts: meson: mark the clock controller also as reset controller
The clock controller provides a few reset lines as well. Add the
corresponding CPU cores.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions