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| author |   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2024-08-18 19:28:35 +0200 |
|---|---|---|
| committer |   Vinod Koul <vkoul@kernel.org> | 2024-08-29 23:46:25 +0530 |
| commit | 45a4237b9be24d6c93db9da2b2180810c5bb2929 (patch) | |
| tree | f4d81275036634b8bb6c0e1d931b8b3578a190f0 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | phy: qcom: qmp-pcie: Add Gen4 4-lanes mode for X1E80100 (diff) | |
| download | wireguard-linux-45a4237b9be24d6c93db9da2b2180810c5bb2929.tar.xz wireguard-linux-45a4237b9be24d6c93db9da2b2180810c5bb2929.zip | |
dt-bindings: phy: socionext,uniphier: add top-level constraints
Properties with variable number of items per each device are expected to
have widest constraints in top-level "properties:" block and further
customized (narrowed) in "if:then:". Add missing top-level constraints
for clock-names and reset-names.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20240818172835.121757-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions