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| author |   Palmer Dabbelt <palmer@rivosinc.com> | 2024-09-20 01:46:50 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-09-20 05:58:08 -0700 |
| commit | 47b9533ccd1a5e9c2e7944686ccf491b27a892f3 (patch) | |
| tree | d8e328d3a9a21bc4fdacf89e0d8075f3e87a4150 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | RISC-V: Don't have MAX_PHYSMEM_BITS exceed phys_addr_t (diff) | |
| parent | tools: Optimize ring buffer for riscv (diff) | |
| download | wireguard-linux-47b9533ccd1a5e9c2e7944686ccf491b27a892f3.tar.xz wireguard-linux-47b9533ccd1a5e9c2e7944686ccf491b27a892f3.zip | |
Merge patch series "tools: Add barrier implementations for riscv"
Charlie Jenkins <charlie@rivosinc.com> says:
Add support for riscv specific barrier implementations to the tools
tree, so that fence instructions can be emitted for synchronization.
* b4-shazam-merge:
tools: Optimize ring buffer for riscv
tools: Add riscv barrier implementation
Link: https://lore.kernel.org/r/20240806-optimize_ring_buffer_read_riscv-v2-0-ca7e193ae198@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions