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author | 2024-02-13 12:48:52 +0200 | |
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committer | 2024-02-26 13:08:45 +0200 | |
commit | 4a5917cd504c7afd5e9de7166eb710687a9b026f (patch) | |
tree | ff7c9450aa2db9af0cd887820ba1157708239158 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | clk: ti: Handle possible address in the node name (diff) | |
download | wireguard-linux-4a5917cd504c7afd5e9de7166eb710687a9b026f.tar.xz wireguard-linux-4a5917cd504c7afd5e9de7166eb710687a9b026f.zip |
clk: ti: Improve clksel clock bit parsing for reg property
Because of legacy reasons, the TI clksel composite clocks can have
overlapping reg properties, and use a custom ti,bit-shift property.
For the clksel clocks we can start using of the standard reg property
instead of the custom ti,bit-shift property.
To do this, let's add a ti_clk_get_legacy_bit_shift() helper, and make
ti_clk_get_reg_addr() populate the clock bit offset.
This makes it possible to update the devicetree files to use the reg
property one clock at a time.
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions