diff options
| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2022-01-10 13:46:48 +0000 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2022-01-24 10:45:14 +0100 |
| commit | 4b4a0fd666303a06bbe159552bc055b490b77cdc (patch) | |
| tree | fbb6c8d43a2ed10ba043e99cce85e08a9a0ced38 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | dt-bindings: arm: renesas: Document Renesas RZ/V2L SoC on SMARC EVK (diff) | |
| download | wireguard-linux-4b4a0fd666303a06bbe159552bc055b490b77cdc.tar.xz wireguard-linux-4b4a0fd666303a06bbe159552bc055b490b77cdc.zip | |
dt-bindings: power: renesas,rzg2l-sysc: Document RZ/V2L SoC
Add DT binding documentation for the SYSC controller found on the RZ/V2L
SoC. This SYSC controller is almost identical to the one found on the
RZ/G2L SoC, the only difference being that SYSC on RZ/V2L has an
additional register to control the DRP-AI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220110134659.30424-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions