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| author |   Mesih Kilinc <mesihkilinc@gmail.com> | 2018-12-02 23:23:50 +0300 |
|---|---|---|
| committer |   Maxime Ripard <maxime.ripard@bootlin.com> | 2018-12-04 08:41:28 +0100 |
| commit | 4ba16d17efdd3bae25863a3e95a4d9b5f52dc686 (patch) | |
| tree | 8021e22b6593cdf93586480e9e100d149c049a1d /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: axp81x: add AC power supply subnode (diff) | |
| download | wireguard-linux-4ba16d17efdd3bae25863a3e95a4d9b5f52dc686.tar.xz wireguard-linux-4ba16d17efdd3bae25863a3e95a4d9b5f52dc686.zip | |
ARM: dts: suniv: add initial DTSI file for F1C100s
F1C100s is one product with the suniv die, which has a 32MiB co-packaged
DDR1 DRAM chip. As we have the support for suniv pin controller and CCU now, add a
initial DTSI for it.
Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions