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author | 2024-06-27 16:39:15 +0200 | |
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committer | 2024-06-27 16:39:16 +0200 | |
commit | 4bd85abedac99b87e6861ad91880661289d4367c (patch) | |
tree | 4802b176b4639555e74cbb5ac21607f102077f42 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | Merge tag 'zynqmp-soc-for-6.11' of https://github.com/Xilinx/linux-xlnx into soc/dt (diff) | |
parent | arm64: dts: socfpga: stratix10: add L2 cache info (diff) | |
download | wireguard-linux-4bd85abedac99b87e6861ad91880661289d4367c.tar.xz wireguard-linux-4bd85abedac99b87e6861ad91880661289d4367c.zip |
Merge tag 'socfpga_dts_updates_for_v6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt
SoCFPGA DTS updates for v6.11
- Drop unneeded flash address
- Add L2 Cache info for Stratix10
* tag 'socfpga_dts_updates_for_v6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: dts: socfpga: stratix10: add L2 cache info
arm64: dts: n5x: socdk: drop unneeded flash address/size-cells
arm64: dts: agilex: socdk: drop unneeded flash address/size-cells
arm64: dts: stratix10: socdk_nand: drop unneeded flash address/size-cells
arm64: dts: stratix10: socdk: drop unneeded flash address/size-cells
Link: https://lore.kernel.org/r/20240626210728.21295-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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