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| author |   Jani Nikula <jani.nikula@intel.com> | 2019-12-11 18:23:47 +0200 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2019-12-19 15:23:59 +0200 |
| commit | 4cb48c447e8753aec2c96630a539eb6207fd6814 (patch) | |
| tree | edafa967394a5eaf1594fb074217cc72b4bcc6f3 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915/dsc: fix DSC register selection for ICL DSI transcoders (diff) | |
| download | wireguard-linux-4cb48c447e8753aec2c96630a539eb6207fd6814.tar.xz wireguard-linux-4cb48c447e8753aec2c96630a539eb6207fd6814.zip | |
drm/i915/dsc: clarify DSC support for pipe A on ICL
The check for cpu_transcoder != TRANSCODER_A is more magic than
necessary, and potentially misleading. Before TGL, DSC is supported on
pipe A if, and only if, it's used with eDP or DSI transcoders. No
functional changes.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/f00e9d55ce20b256177222588780c660aa587cc3.1576081155.git.jani.nikula@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions