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| author |   Sunyeal Hong <sunyeal.hong@samsung.com> | 2024-08-22 08:26:50 +0900 |
|---|---|---|
| committer |   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2024-08-23 09:20:52 +0200 |
| commit | 4d06000979cda26e914552d486e5364248025fcd (patch) | |
| tree | 0fbaced8e9af46dcd756ff42bd092a268b9b8961 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Merge branch 'for-v6.12/clk-dt-bindings' into next/dt64 (diff) | |
| download | wireguard-linux-4d06000979cda26e914552d486e5364248025fcd.tar.xz wireguard-linux-4d06000979cda26e914552d486e5364248025fcd.zip | |
arm64: dts: exynosautov920: add initial CMU clock nodes in ExynosAuto v920
Add cmu_top, cmu_peric0 clock nodes and
switch USI clocks instead of dummy fixed-rate-clock.
Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com>
Link: https://lore.kernel.org/r/20240821232652.1077701-3-sunyeal.hong@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions