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| author |   Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2017-04-20 21:51:35 +0300 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2017-07-27 16:28:32 +0200 |
| commit | 51982d8f4722d1bbc2dabd79d4a1acebb90f6357 (patch) | |
| tree | 0ce120f6ce9f288ee07fe4bf20a4f4898f0789e7 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: sk-rzg1m: add SCIF0 pins (diff) | |
| download | wireguard-linux-51982d8f4722d1bbc2dabd79d4a1acebb90f6357.tar.xz wireguard-linux-51982d8f4722d1bbc2dabd79d4a1acebb90f6357.zip | |
ARM: dts: sk-rzg1m: add Ether pins
Add the (previously omitted) Ether/PHY pin data to the SK-RZG1M board's
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions