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authorIlpo Järvinen <ilpo.jarvinen@linux.intel.com>2023-09-15 18:57:47 +0300
committerBjorn Helgaas <bhelgaas@google.com>2023-10-10 16:03:51 -0500
commit52d92516cb2e04a9b1b8837079a561ca672c1d5e (patch)
tree1e1fbf76d8b780ce1e90e6866e83ae2f3f339d4f /tools/perf/scripts/python/export-to-postgresql.py
parentPCI: Add PCI_L1SS_CTL2 fields (diff)
downloadwireguard-linux-52d92516cb2e04a9b1b8837079a561ca672c1d5e.tar.xz
wireguard-linux-52d92516cb2e04a9b1b8837079a561ca672c1d5e.zip
PCI/ASPM: Use FIELD_GET/PREP() to access PCIe capability fields
Replace open-coded variants to access PCIe capability registers fields with FIELD_GET/PREP(). Link: https://lore.kernel.org/r/20230915155752.84640-3-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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