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author | 2023-03-23 18:01:26 -0500 | |
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committer | 2023-03-31 15:27:36 +0300 | |
commit | 5fe6ec93f10b0765d59e0efb6ecba419a6a49d48 (patch) | |
tree | 701a6029b4242ec98c304a84632ddca3fde693c7 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | clk: imx: Add imx8m_clk_hw_composite_flags macro (diff) | |
download | wireguard-linux-5fe6ec93f10b0765d59e0efb6ecba419a6a49d48.tar.xz wireguard-linux-5fe6ec93f10b0765d59e0efb6ecba419a6a49d48.zip |
clk: imx8mm: Let IMX8MM_CLK_LCDIF_PIXEL set parent rate
By default the display pixel clock needs to be evenly divide
down from 594MHz which rules out a significant number of
resolution and refresh rates.
The current clock tree looks something like:
video_pll1 594000000
video_pll1_bypass 594000000
video_pll1_out 594000000
lcdif_pixel 148500000
Now that composite-8m supports determine_rate, we can allow
lcdif_pixel to set the parent rate which then switches
every clock in the chain to a new frequency when lcdif_pixel
cannot evenly divide from video_pll1_out.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230323230127.120883-4-aford173@gmail.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions