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| author |   Paul Hsieh <paul.hsieh@amd.com> | 2024-05-28 14:36:00 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2024-06-19 14:17:25 -0400 |
| commit | 6071607bfefefc50a3907c0ba88878846960d29a (patch) | |
| tree | 3bc21743c8097cbebe8e9b93245e4c7deea05326 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/amd/display: Change dram_clock_latency to 34us for dcn351 (diff) | |
| download | wireguard-linux-6071607bfefefc50a3907c0ba88878846960d29a.tar.xz wireguard-linux-6071607bfefefc50a3907c0ba88878846960d29a.zip | |
drm/amd/display: change dram_clock_latency to 34us for dcn35
[Why & How]
Current DRAM setting would cause underflow on customer platform.
Modify dram_clock_change_latency_us from 11.72 to 34.0 us as per recommendation from HW team
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Paul Hsieh <paul.hsieh@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions